1. Field of the Invention
The present invention relates to a method and apparatus for performing floating point division in general and in particular to a method and apparatus for saving machine cycles that would otherwise generate leading zero quotient bits during a floating point division operation.
2. Description of Prior Art
A typical floating point number such as used in the IBM 370 architecture comprises a sign bit, 7 characteristic or exponent bits and either 6 or 14 mantissa or fraction hexadecimal digits. Six fraction digits are used in short division and 14 fraction digits are used in long division when greater accuracy is desired. When binary coded, a hexadecimal digit comprises 4 bits. For example, a hexadecimal 96, or 96.sub.16, is represented in binary as 1001 0110.
In typical prior known floating point division operations in which a dividend N was divided by a divisor D in a binary arithmetic logic unit, the fractions of the dividend and the divisor N and D, FRAC(N) and FRAC(D), respectively, were initially normalized to eliminate zeros in the leading most significant digit positions. For example, a hexidecimal dividend N=16.sup.3 .times.0.00321 after being normalized was represented as 16.sup.1 .times.0.321. Note that for each leading zero that was eliminated, the exponent of the radix 16 was adjusted accordingly.
After FRAC(N) and FRAC(D) were normalized, FRAC(N) was further adjusted so that EQU FRAC(N)&lt;FRAF(D),
any accompanying exponent was adjusted accordingly and a bit trigger register was set or reset depending on the nature of the adjustment to FRAC(N), as further described below. The purpose of making sure that FRAC(N) was less than FRAC(D) at the outset of the division operation was to insure that all digits in FRAC(N) and FRAC(D) would participate in the division operation.
Three examples will illustrate the adjustments to FRAC(N) which were heretofore made to comply with the requirement that EQU FRAC(N)&lt;FRAC(D)